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Showing posts with label 3rd Semester ECE16. Show all posts
Showing posts with label 3rd Semester ECE16. Show all posts

Friday, September 9, 2016



Roll No.
Total No. of Questions : 091
B.Tech. (Sem. – 3rd)
ELECTRONICS DEVICES & CIRCUITS
SUBJECT CODE : EC - 201
Paper ID : [2126]
Time : 03 Hours
Instruction to Candidates:
1) Section - A is Compulsory.
2) Attempt any Four questions from Section - B.
3) Attempt any Two questions from Section - C.

Section - A
Ql)

a)     Draw the Ideal characteristics of the Diode.

b)    With the characteristic curves & write briefly about working of photo diode.

c)     Write the advantages of MOSFET.

d)    In a fixed bias circuit

RB =150kΩ, RC. = 2kΩ, VCC = l2V,Transistor is silicon with B=100
then find ‘iB’.

e)     Write the advantages of class 'AB' amplifier.

f)      In what type of applications tuned coupling are used. ..

g)     What is meant by feed back? What type of feed back is used in oscillator.

h)    write the characteristics of current shunt feedback amplifier.

i)       Draw and explain the general tank circuit of LC oscillator.

j)       Expl4rn Thermal Runway.
section-B

 Q2) (a) In a diode how the carrier is developed.

(b) Draw the equivalent circuit of Junction Diode
.
Q3) Draw the hybrid model of a low frequency small signal voltage Amplifier.

Q4) Draw and explain the V-I characteristics of JFET.

Q5) A silicon transistor uses potential divider method of Biasing V.. = 12V

R1 = 10 kΩ, R2 = 5 kΩ, R1 = 1 kΩ and RE = 3 kΩ. Determine the operating point using The venin’s theorem.

 Q6) For class A, CE, amplifier circuit shown in Figure (VCE)r=10V and

(IC ), =500mA. If the output current varies by +250mA when an input signal  is applied at the Base, compute the collector efficiency and over all efficiency.


Section - C

Q7) (a) Why the transistor circuit requires stabilization?

(b) Derive the stability factor(s) for voltage division method.

Q8) (a) Draw the circuit of a class 'B' push-pull amplifier and explain its operation

(b) Derive the voltage distortion in push-pull amplifier.

Q9 Derive the expression for the frequency of oscillations and condition for sustain oscillations in a Colpitt’s oscillator.



Electronic Devices & Circuits
(EC-201, DEC-2005)

Note: Section A is compulsory. Attempt any four questions from Section B and any two questions from  Section C.
Section-A
1.
(a) What is the main important difference between the characteristics of a simple switch and those  of an ideal diode?
(b) Compare JFET and MOSFET. Mention at least four points.
(c) What is reverse Recovery Time?
(d) A dc voltage supply provides 60V when output is unloaded. When connected to a load the  output drops to 56V. Calculate the values of voltage regulation.
(e) What is “Dark current” of a photodiode?
(f) What is negative resistance region?
(g) Which two methods makes the collector current constant. Explain them.
(h) What is fold back limiting?
(i) Calculate dc voltage across 1 Kr load for a RC filter (R=120r, C=10m F). The dc voltage across  the initial filter capacitor is 60V.
(j) Draw the piecewise linear equivalent circuit of diode and explain it briefly.

Section-B

2. Explain the working of CMOS Invertor. Also mention the applications and advantages over other  approaches.
3.

(a) Describe the differences between re and hybrid equivalent for a BJT transistor.
(b) For each model, list the conditions under which it should be applied.

4. A full wave bridge rectifier with 120V rms sinusoidal input has a load resistor of 1kΩ.
 (i) If silicon diodes are employed, what is dc voltage available at load?
 (ii) Determine required PIV rating of each diode.
 (iii) Find maximum current through each diode during condition.
 (iv) What is required power rating of each diode?
5. A silicon transistor with β = 100 is to be used in self biasing circuit shown in figure below, such        that  the Q-point corresponds to VCE = 12V and IC = 2m A. Find RE if VCC = 24V and RC = 5KΩ.
Fig.
6.
(a) What is Miller Theorem?
(b) Explain analysis of emitter follower by using this theorem.

Section-C

7.

(a) What is the significant difference between the construction of an enhancement-type MOSFET  and a depletion type MOSFET?

(b) Sketch the circuit of a CS amplifier. Derive the expression for the voltage gain at low  frequencies.

8.
 (a) For a zener diode network shown in below fig. Determine VL , VR, IZ and PZ.

 (b) What do you mean by hot carrier diode? Compare the characteristics of hot carrier and p-n junction diode?
Fig.
9.

 (a) Design a self-bias network using a JFET transistor with IDSS = 8m A and VP = -6V to have a Qpoint at IDQ = 4m A using a supply of 14V. Assume the RD = 3RS and use standard values.


 (b) Discuss the three configurations of FET biasing. Explain any one in detail.





Roll No.
Total No. of Questions : 091
B.Tech. (Sem. - 3'd)
ELECTRONICS DEVICES & CIRCUITS
SUBJECT CODE : EC - 201
Paper ID : [A0301]
Time : 03 Hours
Instruction to Candidates:
1) Section - A is Compulsory.
2) Attempt any Four questions from Section - B.
3) Attempt any Two questions from Section - C.

Section - A
Q1)

 a) State what do you understand barrier potential across PN junction and also explain its                          significance.

b) Why bridge type rectifier is preferred over a center tap rectifier?

c) How a PN junction posses a capacitance?

d) What do you understand by the collector reverse saturation current?

e) Why an ordinary junction transistor is called bipolar?

f) What is the need of biasing in a transistor?

g) Draw the h-parameter equivalent circuit of,a transistor.

h) What are characteristics of a good amplifier?

i) In what respect FETs better than BJTs?

j) Define all important parameters of JFET.

Section-B

Q2) The load resistance of a centre tapped full wave rectifier is 500fJ and the
necessary voltage is 60 sin(100t). Calculate
(a) peak, average and rms value of current.
(b) ripple factor and
(c) efficiency of the rectifier.
Each diode has an idealized V-I characteristic having slope corresponding to a resistance of 50Ω

Q3) Explain how stabilization of operating point is achieved using potential divider biasing circuit.

Q4) Draw the output characteristics of JFET and explain how it works as a voltage controlled device.

Q5) Disuses analysis of transistor amplifier using h-parameter in CB configuration?

Q6) The interbase resistance for a silicon UJT is 8k â„¦ and RB1 = 5k â„¦ with IE = 0.

Determine

(a) Rs2 and (b) intrinsic stand-off ratio.

Determine UJT current, stand-off voltage and peak point voltage when a voltage of 15V is applied between the bases. Take VB = 0.7V.

Section - C

Q7) (a) Draw and explain the drain and transfer characteristics of an n-channel
enhancement MOSFET.

(b) Sketch the circuit of a CS amplifier. Derive the expression for the voltage
gain at low frequencies.

Q8) Define h-parameters. Derive expression for

(a) Voltage gain

(b) Current gain

(c) Input resistance

(d) Output resistance of CE amplifiers using h-parameters.

Q9) Write short notes on two of the following :

(a) Photransister

(b) FET as an amplifier


(c) Miller's theorem.



Electronic Circuits and Devices
(EC-201, Dec-07)

Section-A
1).

 a). Discuss the behavior of p-n junction diode under forward and reverse biased
conditions.
b). Draw circuit diagram for CC and CE configuration of transistor. Which is having  higher gain and why.
c). State advantages of JFET over BJT.
d). What is operating point? Why is it necessary to stabilize operating point of a
transistor amplifier?
e). What do you understand by class A,B and C power amplifiers.
f). Draw the block diagram of a multistage amplifier having n-stages. Write
expression for its gain (A).
g). State advantages of –ve feedback in amplifiers.
h). What is an oscillator? What are the essential components of feed back LC
oscillator?
i). Differentiate between photo diodes and photo transistor.
j). Define term junction capacitance. Name different type of capacitances diode
posses.
Section-B

2). Define stability factor. Explain with circuit diagram of potential divider method of  biasing in amplifiers.

3). Draw the circuit diagram of a push pull amplifier. Explain its operation. Discuss advantages and disadvantages.

4). What do you mean by coupling of two amplifier stages. Explain with requisite circuit  diagrams the resistance-capacitance coupling scheme.

5). Draw the block diagram of negative feed back amplifier. Derive an expression for the voltage gains of an amplifier of gain (A) when subjected to negative feedback (B).

6). Explain the principal of working of transistor Hartley oscillator. Draw circuit diagram and briefly function of each component.
Section-C

7). Define h-parameters. Derive expression for

 (a) Voltage gain (b) Current gain (c) Input resistance
 (d) Output resistance of CE amplifiers using h-parameters

8). (a) Draw labeled diagram showing constructional features of N-channel MOSFET. Explain principle and working of N-channel MOSFET in briefly explain.

      (b) Distortion in amplifier circuits.

9). Write short notes on two of the following:-

 (a) Thermal runway (d) PIN Diodes

 (c) Effect of –ve feed back on output resistance of an amplifier.

Thursday, September 8, 2016


Roll no ..........
Total No. Of questions: 9]
EC -205
DIGITAL ELECTONICS
(B.Tech. 3rd Semester , 5001)

Note :- This paper consist of Three SECTIONS. Section A is compulsory.  Do any four questions from section B and any Two question from Section c.
1.                   
a.                 What is Positive Logic and Negative Logic?
b.                 Draw the truth table of al Logic gates.
c.                  Realize an And gate using Nor gates only.
d.                 What is the difference between multiplexer
e.                   Give comparison between various A-D conceders.
f.                   What is Base Current Hogging? How as it eliminated?
g.                 What is a Register? List various methods of loading the data into shift register.
h.                 What is the difference between CAM and RAM
i.                   How race around condition is eliminated in Master-Slave J-K flip-flop?
j.                   Perform the following binary subtraction:

           0101010-11010101.

Section –B

2.                 Draw the truth table of a full Subtractor Circuit. Realize the full Subtractor circuit using NOR            gates only.

3.                 Draw the diagram of parallel Comparator A-D converter and explain its operation.

4.                 Minimize the following Boolean expression using K-Map;

           F (w,x,y,z) = (4,5,8,12,13,14,15)

5.                 What is a content addressable memory? How it helps in locating the data at fast speed?

6.                 Draw the circuit of an ECL gate and explain its operation.

Section –C

7.                 Determine the minimal sum-of –products expression for the following Boolean function:
            M (8,12,13,18,19,21,22,24,25,28,31)+dc (1,2,3,6,7,11).

8.                 Design a Synchronous counter to count in the following sequence using J-K flip-flops :                        15,14,13,12,11,10,9,15. Your design should avoid lock –out condition.

9.                    
a.                 Design a four bit parity checker circuit and realize it.

b.                How many 128 x 8 chips are needed to provide a memory capacity of 2048 bytes?             How many address lines must be used to access 2048 bytes?

c.                  Write a short note on memory organization.







Roll no ...........
Total No. Of Questions : 9]
EC-205
Digital Electronics
(B.Tech., 3rd Semester, 2063)
Time : 3 hrs
Note – This paper consists of Three Sections. Sections   A is compulsory. Answer any four questions from Section –B and any Two questions from Section C.

Section –A
1.                 Answer briefly the following questions:

a.                 Give the binary and hexadecimal equivalent of decimal number (492.75).

b.                 Perform the subtractions 73-117 using 2 ‘s complement method.

c.                  Simplify the Boolean expression:
           F = D(A+C) (A+BD)+ACD,
           Using logic rules.

d.                 Write the truth take of a 3-input XOR gate.

e.                  Find the simplified POS form of faction
            F(X,Y,Z) =Æ© (0,1,3,7) 

f.                   Simplify the faction

            F(w,x,y,z) =m4+m5+m7+m8+m9+m11+m12+m15)

           Using K- map

g.                 Differentiate between demultiplexer and decoder.

h.                 Implement a full subtract or with two 4:1 multiplexers.

i.                   Differentiate between static RAM and dynamic RAM.

j.                   Make comparisons of TTL and ECL logic families.

Section –B

2.                 Design a Excess-3 to BCD code converter using minimum number of NAND gates.
3.                 Represent the Boolean expression:

          F(A,B,C) = (A+C) (B+C)(A+B)

          In its canonical POS and SOP forms.

4.                 Explain the operation of Master/Slave J-K flip-f lop. List its advantages.
5.                 Describe the working of successive approximation A/D converter.
6.                 Construct a 4-bit asynchronous up/down counter and explain its working with the help of 
            timing diagram.

Section –C

7.                 Minimize the Boolean expression :

           F(A,B,C,D,E) = M (6,7,11,13,14,17,20,25,28,29,30)

8.                 Design a  mod 5 counter and, hence, construct the logic diagram of a decade counter.

9.                   

a.                 Design a combination circuit that compares two 2-bit numbers A and B for equality.

b.                 Explain briefly the charge –coupled device (CCD ) memory.   



9129
B.TECH. 3RD SEMESTER
EC-205- DIGITAL ELECTORNICS
Time :3 hrs
Note : This paper consists of three sections. Section A is compulsory. Attempt any four questions form section B and two form Section C.
1.                  
a.                 List the advantages of  hexadecimal number system.
b.                 How will you detect overflow in signed-magnitude and Z’s complement integer additions.
c.                  Realize a z –input XOR gate using NAND gates only.
d.                 Simplify(A.B(C+B.D)+ A,B.) C.
e.                  What is meant by CAM ?
f.                   What do you understand by ‘race condition’ in flip-flops?
g.                 How many bits will a D/A converter use so that its full-scale output voltage is 5V and its resolution is at the most 10mv.

h.                 Name the four triggering methods.

i.                   Define ‘propagation delay time’ and ‘figure of merit’

j.                   What are advantages of CMOS logic family over other logic families.

Section –B

2.                 Minimize the function using K-map method and implement the same using NAND/NOR 
           gates. F(A,B,C,D) = TTM (1,2,3,8,9,10,11,14). D(7,15)

3.                 What is a ROM? What are the different types of ROMs? Give the characteristics features of 
            each.

4.                 What is PLA? Design a  BCD to excess- 3 code converter using PLA.

5.                 Draw the circuit of a 3 – input ECL nor gate & discuss its operation what is the primary 
            advantages of ECL gate.

6.                 Devise a method of measuring frequency by means of a counter. Draw the circuit.

Section –C

7.                   

a.                 Convert a given Dflip- flop to a JK flip flop.
b.                 Discuss weighted resistor D/A converter.

8.                   
a.                 Design a synchronous mod – 6counter.

b.                 Realize the expression

F(a,b,c,d) = Ʃm(0,2,3,6,8,9,12,14) using a 8:1 multiplexer and an inverter

9.                   
a.                 Design a parity generator to generate an odd parity bit for a 4-bit word(Use minimum number of gates)

b.                 Define a Register. Construct a shift register form RS flip-flops and explain their operation.






9129
B.TECH. 3RD SEMESTER
EC-205- DIGITAL ELECTORNICS
Time :3 hrs
Note : This paper consists of three sections. Section A is compulsory. Attempt any four questions form section B and two form Section C.

1.                  
a.                 List the advantages of  hexadecimal number system.
b.                 How will you detect overflow in signed-magnitude and Z’s complement integer additions.
c.                  Realize a z –input XOR gate using NAND gates only.
d.                 Simplify(A.B(C+B.D)+ A,B.) C.
e.                  What is meant by CAM ?
f.                   What do you understand by ‘race condition’ in flip-flops?
g.                 How many bits will a D/A converter use so that its full-scale output voltage is 5V and its 
            resolution is at the most 10mv.
h.                 Name the four triggering methods.
i.                   Define ‘propagation delay time’ and ‘figure of merit’
j.                   What are advantages of CMOS logic family over other logic families.

Section –B

2.                 Minimize the function using K-map method and implement the same using NAND/NOR 
            gates. F(A,B,C,D) = TTM (1,2,3,8,9,10,11,14). D(7,15)

3.                 What is a ROM? What are the different types of ROMs? Give the characteristics features of 
           each.

4.                 What is PLA? Design a  BCD to excess- 3 code converter using PLA.

5.                 Draw the circuit of a 3 – input ECL nor gate & discuss its operation what is the primary 
            advantages of ECL gate.

6.                 Devise a method of measuring frequency by means of a counter. Draw the circuit.

Section –C
7.                   
a.                 Convert a given Dflip- flop to a JK flip flop.
b.                 Discuss weighted resistor D/A converter.
8.                   
a.                 Design a synchronous mod – 6counter.
b.                 Realize the expression

           F(a,b,c,d) = Æ©m(0,2,3,6,8,9,12,14) using a 8:1 multiplexer and an inverter

9.              
      
a.                 Design a parity generator to generate an odd parity bit for a 4-bit word(Use minimum number            of gates)
b.                 Define a Register. Construct a shift register form RS flip-flops and explain their operation.





Digital Electronics
(EC-205, DEC-2005)
Note: Section A is compulsory. Attempt any four questions from Section  and any two questions from  Section C.
Section-A

a) What is Excess-3 and Gray code?
b) Why ASCll-code is a 7-bit code?
c) Add (7F)16 & (BA)16.
d) Differentiate between half and full subtractors.
e) Compare a decoder with a demultiplexer.
f) What is meant by a state diagram?
g) What is meant by ‘accuracy’ of and A/D/converter
h) Difference between PLA and ROM?
i) Explain the problem of ‘current hogging’ in DCTL.
j) Explain the operation of CMOS(NOR gate).

Section-B

2. Represent the following decimal numbers in twos complement format:
 i) +3           ii) +25         iii) –5          iv) –11        v) –9

3. Write the full name in :a) ASCll code b) EBCDIC code c) Excess –3 code

4. Minimize the following function and realize using minimum no of gates:

 f1 = -Σm(0,3,5,6,9,10,12,15)

5. Design a BCD to Excess-3 code converter using minimum no of NAND gates

6. Design a four bit subtract or using four bit adder and minimum no of EX-OR gates.

Section-C

7. Obtain the output wave forms of a 5-stage ring-counter. Draw its state diagram

8. Explain the following codes and give example using four bits.

 a) CSB b)COB c)CTC d) CCD

9. Explain & compare the following with its block diagram.

a) Linear selection addressing


b) Coincidence selection addressing

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