Digital Circuit And Logic Design Question Paper of 3rd Semester ECE16 Download Previous Years Question Paper 1

Roll No.

Total No. of Questions : 09

B.Tech. (ECE/ETE) (Sem.–3)

DIGITAL CIRCUIT AND LOGIC DESIGN

Subject Code : BTEC-302 (2011 Batch)

Paper ID : [A1131]

Time : 3 Hrs.

INSTRUCTION TO CANDIDATES :

1. SECTION-A is COMPULSORY consisting of TEN questions carrying

TWO marks each.

2. SECTION-B contains FIVE questions carrying FIVE marks each and

students has to attempt any FOUR questions.

3. SECTION-C contains THREE questions carrying TEN marks each and

students has to attempt any TWO questions.

SECTION-A

l. Write briefly :

(i) What is the difference between combinational and sequential circuits?

(ii) What is race around condition and how it is removed?

(iii) Explain the propagation delay time in DTL.

(iv) Subtract using 9's, 10's, 2's and 1 's complement (18-24).

(v) (3C5)16 – (1F7)16 = (-----)16 and (235) ₈ + (146)₈ = (--------)₈

(vi) Explain the D flip-flop and importance of preset and clear function.

(vii) Explain resolution and accuracy of A/D converter.

(viii) What is the difference between multiplexer and encoder?

(ix) What is the difference between static and dynamic memory?

(x) What is binary ladder network and its importance?

SECTION-B

2. Explain the working of JK flip-flop using truth table and also derive excitation table of JK FF from characteristic table.

3. Explain 3 bit Asynchronous DOWN-counter with the help of waveform. Design MOD-14 Asynchronous up counter using JK flip-flop.

4. Design Full adder and Full substractor circuit using 4 to 1 MUX

5. Explain the working of simultaneous and Dual slope A/D converter.

6. Solve using K map and implement result with the help of NAND gates 

    

    only F(A,B,C,D) = ACD+ABD+ACD+AB+ABC

SECTION-C

7. (a) Design BCD to grey code converter combinational circuit.

    (b) Explain 2-input CMOS NOR gate.

8. Design MOD-6 up-down counter by avoiding lock out conditions using JK Flip-flop.

9. Explain 2-Input NAND and NOR gate of TTL logic family.