Digital Circuit And Logic Design Question Paper of 3rd Semester ECE16 Download Previous Years Question Paper 4

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Total No. of Questions : 09

B.Tech. (ECE/ETE) (Sem.–3)

DIGITAL CIRCUIT AND LOGIC DESIGN

Subject Code : BTEC-302

Paper ID : [A1131]

Time : 3 Hrs.

INSTRUCTION TO CANDIDATES :

INSTRUCTIONS TO CANDIDATE:

1. Section –A, is Compulsory.

2. Attempt any four questions from Section-B.

3. Attempt any two questions from Section-C.

Section A

1.                   

a.                 Convert (472.325)₈ to decimal and binary.

b.                 Generate a 3-bit Gray code.

c.                  Determine logic required to decode binary number(1011)₂ by giving high indication on                       output.

d.                 When and where do we use open –collector operation ?

e.                  Determine  conversion time of Successive – approximation ADC for a 12- bit resolution at 2.5             MHz .

f.                   Draw and explain the circuit diagram and truth table for a SR flip-flop.

g.                 What is the most widely used method of representing binary numbers and performing                           arithmetic in computer systems?

h.                 Simplify and implement the expression using Boolean algebra

i.                        Y = A’B’C + A’BC + ABC

j.                   How the information is transferred into and out of a register?

k.                   Define a gate and discuss its types. Convert NAND to NOR gate.

Section –B

2.                  Minimize and implement four variable switching function using Q-M tabulation method

a.                 F (A, B, C, D) =  Ʃ(0,1,2,3,4,6,8,9,10,11)

3.                 Differentiate between serial loading and parallel loading for a shift –register.

4.                 Describe how the problem of variable load is overcome by using  i often –pole arrangement?

5.                 Design a 3-bit binary to octal decoder

6.                 Explain the operation of a Parallel encoded Analog to digital converter.

Section –C

7.                Design a Down counter. That counts in the sequence of 6-5-4-3-2-6-5-4-3-2-6-5, and so on                  using Jk filp-flop

8.                   

a.                 How will you convert a D flip –flop into a JK flip – flop

b.                 Describe search operation in CAM.

9.                   

a.                 Explain how a programmable ROM is formed.

b.                 What is the difference  between PLA and PLA? Explain PAL in detail .

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Digital Circuit And Logic Design Question Paper of 3rd Semester ECE16 Download Previous Years Question Paper 3

Roll No.

Total No. of Questions : 09

B.Tech. (ECE/ETE) (Sem.–3)

DIGITAL CIRCUIT AND LOGIC DESIGN

Subject Code : BTEC-302 (2011 Batch)

Paper ID : [A1131]

Time : 3 Hrs.

INSTRUCTION TO CANDIDATES :

1. SECTION-A is COMPULSORY consisting of TEN questions carrying

TWO marks each.

2. SECTION-B contains FIVE questions carrying FIVE marks each and

students has to attempt any FOUR questions.

3. SECTION-C contains THREE questions carrying TEN marks each and

students has to attempt any TWO questions.

SECTION-A

l. Answer briefly :

a) Convert (10110110)2 to Gray code and Excess 3 code.

b) Prove that if A+B = A+C and AB=AC then B=C.

c) Give the implementation circuit of 3 to 8 line decoder.

d) Compare sequential circuits and combinational circuits.

e) Convert the following logic function into product of midterms :

F(A,B,C,D) = C’D+ABC’+A’B’D+ABD’

f) How many bits are required for a DAC so that its full scale output is

12.6 V and resolution is 20 mV?

g) Implement the following function using PAL: Y=  m(2,4).

h) List different applications of counters.

i) Explain resolution of A/D converters.

j) Give the classification of Bipolar and Unipolar logic families.

SECTION-B

2. Simplify using K maps :

I) Y= ∑ m(l,3,5,6) + ∑ d(4)

II) Y= ∑M (1,3,7,11,15 ). d(5,9,13)

3. Design a 3 bit odd parity generator.

4. Convert JK Flip flop to SR flip flop.

5. What are three basic types of TTL? Explain any two in detail.

6. Explain briefly working of binary weighted resistance D/A converter with the help of an example. What are its drawbacks?

SECTION-C

7. Write short notes on :

I) PLD’s

II) ROM.

8. a) Design a 3 bit synchronous up/down counter using JK flip flops.

b) Explain two applications of registers as counters.

9. Enlist different applications of Multiplexer. Implement the logic function:

Y(A,B,C,D)=  m(0,l,3,5,7) using

I) Single 8:1 MUX

II) Single 4:1 MUX

III) Single 2:1 MUX

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Digital Circuit And Logic Design Question Paper of 3rd Semester ECE16 Download Previous Years Question Paper 2

Roll No.

Total No. of Questions : 09

B.Tech. (ECE/ETE) (Sem.–3)

DIGITAL CIRCUIT AND LOGIC DESIGN

Subject Code : BTEC-302

Paper ID : [A1131]

Time : 3 Hrs.

INSTRUCTION TO CANDIDATES :

INSTRUCTIONS TO CANDIDATE:

1. Section –A, is Compulsory.

2. Attempt any four questions from Section-B.

3. Attempt any two questions from Section-C.

Section A

Ql. a) If A= (101)2 , B= (110)2,find A-B.

b) Convert Y= ∑m (l,3,5) into Standard SOP and POS form

c) Implement half adder using NAND gates

d) Compare synchronous counters and asynchronous counters.

e) What is a Register? Give its ‘different types.

f) Define i) Noise Margin i) Fan in.

g) List various types of RAM and ROM.

h) Which type of circuit is used for edge triggering? Give its arrangement for positive and negative triggering.

i) A counter type A/D converter contains a 4 bit binary ladder and is driven by 2 MHz clock calculate conversion rate and resolution?

j) Explain: PAL and PLA.

Section B

Q2. A combinational circuit has 3 inputs A,B and C and output F. F is true for following input                    combinations:

A is False and B is True; A is False and C is True; A, B, C are False; A,B, C are True.

a) Write the Truth. Table for F

b) Write the simplified expression for F in SOP form and POS form

c) Draw the logic circuit using NOR gates.

Q3. a) Implement Y(A,B,C,D) = ∑m (1,3,5,7,9,1,14) using 4:1 MUX.

b) Design 4x16 decoder with 2x4 decoder.

Q4. a) Convert SR to D flip flop

       b) Explain briefly how Race around conditon in flip flop is avoided

Q5. Discus different specifications of A/D converter.

Q6. What is a memory cel? Discus different RAM cells and ROM cells.

Section-C

Q7. Simplify the following functions using K map and implement he circuit using NAND gates only:

(a) Y = ∑m(2,3,4,5,13,15) + ∑d(8,9,10,l 1)

(b) S = ∑ m (1, 5, 7, 8, 9, 10, 1, 14, 15)

Q8. With neat diagram explain the working of

a) 4 bit serial in serial out shift register

b) 2 bit Asynchronous Ripple Up counter

Q9. Discus MOS logic family in brief.

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Digital Circuit And Logic Design Question Paper of 3rd Semester ECE16 Download Previous Years Question Paper 1

Roll No.

Total No. of Questions : 09

B.Tech. (ECE/ETE) (Sem.–3)

DIGITAL CIRCUIT AND LOGIC DESIGN

Subject Code : BTEC-302 (2011 Batch)

Paper ID : [A1131]

Time : 3 Hrs.

INSTRUCTION TO CANDIDATES :

1. SECTION-A is COMPULSORY consisting of TEN questions carrying

TWO marks each.

2. SECTION-B contains FIVE questions carrying FIVE marks each and

students has to attempt any FOUR questions.

3. SECTION-C contains THREE questions carrying TEN marks each and

students has to attempt any TWO questions.

SECTION-A

l. Write briefly :

(i) What is the difference between combinational and sequential circuits?

(ii) What is race around condition and how it is removed?

(iii) Explain the propagation delay time in DTL.

(iv) Subtract using 9's, 10's, 2's and 1 's complement (18-24).

(v) (3C5)16 – (1F7)16 = (-----)16 and (235) ₈ + (146)₈ = (--------)₈

(vi) Explain the D flip-flop and importance of preset and clear function.

(vii) Explain resolution and accuracy of A/D converter.

(viii) What is the difference between multiplexer and encoder?

(ix) What is the difference between static and dynamic memory?

(x) What is binary ladder network and its importance?

SECTION-B

2. Explain the working of JK flip-flop using truth table and also derive excitation table of JK FF from characteristic table.

3. Explain 3 bit Asynchronous DOWN-counter with the help of waveform. Design MOD-14 Asynchronous up counter using JK flip-flop.

4. Design Full adder and Full substractor circuit using 4 to 1 MUX

5. Explain the working of simultaneous and Dual slope A/D converter.

6. Solve using K map and implement result with the help of NAND gates 

    

    only F(A,B,C,D) = ACD+ABD+ACD+AB+ABC

SECTION-C

7. (a) Design BCD to grey code converter combinational circuit.

    (b) Explain 2-input CMOS NOR gate.

8. Design MOD-6 up-down counter by avoiding lock out conditions using JK Flip-flop.

9. Explain 2-Input NAND and NOR gate of TTL logic family.

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