Digital Electronics Question Paper of 3rd Semester ECE16 Download Previous Years Question Paper 5

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Total No. Of questions: 9]

EC -205

DIGITAL ELECTONICS

(B.Tech. 3^rd Semester , 5001)

Note :- This paper consist of Three SECTIONS. Section A is compulsory.  Do any four questions from section B and any Two question from Section c.

1.                   

a.                 What is Positive Logic and Negative Logic?

b.                 Draw the truth table of al Logic gates.

c.                  Realize an And gate using Nor gates only.

d.                 What is the difference between multiplexer

e.                   Give comparison between various A-D conceders.

f.                   What is Base Current Hogging? How as it eliminated?

g.                 What is a Register? List various methods of loading the data into shift register.

h.                 What is the difference between CAM and RAM

i.                   How race around condition is eliminated in Master-Slave J-K flip-flop?

j.                   Perform the following binary subtraction:

           0101010-11010101.

Section –B

2.                 Draw the truth table of a full Subtractor Circuit. Realize the full Subtractor circuit using NOR            gates only.

3.                 Draw the diagram of parallel Comparator A-D converter and explain its operation.

4.                 Minimize the following Boolean expression using K-Map;

           F (w,x,y,z) = (4,5,8,12,13,14,15)

5.                 What is a content addressable memory? How it helps in locating the data at fast speed?

6.                 Draw the circuit of an ECL gate and explain its operation.

Section –C

7.                 Determine the minimal sum-of –products expression for the following Boolean function:

            M (8,12,13,18,19,21,22,24,25,28,31)+dc (1,2,3,6,7,11).

8.                 Design a Synchronous counter to count in the following sequence using J-K flip-flops :                        15,14,13,12,11,10,9,15. Your design should avoid lock –out condition.

9.                    

a.                 Design a four bit parity checker circuit and realize it.

b.                How many 128 x 8 chips are needed to provide a memory capacity of 2048 bytes?             How many address lines must be used to access 2048 bytes?

c.                  Write a short note on memory organization.

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Digital Electronics Question Paper of 3rd Semester ECE16 Download Previous Years Question Paper 4

Roll no ...........

Total No. Of Questions : 9]

EC-205

Digital Electronics

(B.Tech., 3^rd Semester, 2063)

Time : 3 hrs

Note – This paper consists of Three Sections. Sections   A is compulsory. Answer any four questions from Section –B and any Two questions from Section C.

Section –A

1.                 Answer briefly the following questions:

a.                 Give the binary and hexadecimal equivalent of decimal number (492.75).

b.                 Perform the subtractions 73-117 using 2 ‘s complement method.

c.                  Simplify the Boolean expression:

           F = D(A+C) (A+BD)+ACD,

           Using logic rules.

d.                 Write the truth take of a 3-input XOR gate.

e.                  Find the simplified POS form of faction

            F(X,Y,Z) =Ʃ (0,1,3,7) 

f.                   Simplify the faction

            F(w,x,y,z) =m₄+m₅+m₇+m₈+m₉+m₁₁+m₁₂+m₁₅)

           Using K- map

g.                 Differentiate between demultiplexer and decoder.

h.                 Implement a full subtract or with two 4:1 multiplexers.

i.                   Differentiate between static RAM and dynamic RAM.

j.                   Make comparisons of TTL and ECL logic families.

Section –B

2.                 Design a Excess-3 to BCD code converter using minimum number of NAND gates.

3.                 Represent the Boolean expression:

          F(A,B,C) = (A+C) (B+C)(A+B)

          In its canonical POS and SOP forms.

4.                 Explain the operation of Master/Slave J-K flip-f lop. List its advantages.

5.                 Describe the working of successive approximation A/D converter.

6.                 Construct a 4-bit asynchronous up/down counter and explain its working with the help of 

            timing diagram.

Section –C

7.                 Minimize the Boolean expression :

           F(A,B,C,D,E) = M (6,7,11,13,14,17,20,25,28,29,30)

8.                 Design a  mod 5 counter and, hence, construct the logic diagram of a decade counter.

9.                   

a.                 Design a combination circuit that compares two 2-bit numbers A and B for equality.

b.                 Explain briefly the charge –coupled device (CCD ) memory.   

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Digital Electronics Question Paper of 3rd Semester ECE16 Download Previous Years Question Paper 2

9129

B.TECH. 3^RD SEMESTER

EC-205- DIGITAL ELECTORNICS

Time :3 hrs

Note : This paper consists of three sections. Section A is compulsory. Attempt any four questions form section B and two form Section C.

1.                  

a.                 List the advantages of  hexadecimal number system.

b.                 How will you detect overflow in signed-magnitude and Z’s complement integer additions.

c.                  Realize a z –input XOR gate using NAND gates only.

d.                 Simplify(A.B(C+B.D)+ A,B.) C.

e.                  What is meant by CAM ?

f.                   What do you understand by ‘race condition’ in flip-flops?

g.                 How many bits will a D/A converter use so that its full-scale output voltage is 5V and its resolution is at the most 10mv.

h.                 Name the four triggering methods.

i.                   Define ‘propagation delay time’ and ‘figure of merit’

j.                   What are advantages of CMOS logic family over other logic families.

Section –B

2.                 Minimize the function using K-map method and implement the same using NAND/NOR 

           gates. F(A,B,C,D) = TTM (1,2,3,8,9,10,11,14). D(7,15)

3.                 What is a ROM? What are the different types of ROMs? Give the characteristics features of 

            each.

4.                 What is PLA? Design a  BCD to excess- 3 code converter using PLA.

5.                 Draw the circuit of a 3 – input ECL nor gate & discuss its operation what is the primary 

            advantages of ECL gate.

6.                 Devise a method of measuring frequency by means of a counter. Draw the circuit.

Section –C

7.                   

a.                 Convert a given Dflip- flop to a JK flip flop.

b.                 Discuss weighted resistor D/A converter.

8.                   

a.                 Design a synchronous mod – 6counter.

b.                 Realize the expression

F(a,b,c,d) = Ʃm(0,2,3,6,8,9,12,14) using a 8:1 multiplexer and an inverter

9.                   

a.                 Design a parity generator to generate an odd parity bit for a 4-bit word(Use minimum number of gates)

b.                 Define a Register. Construct a shift register form RS flip-flops and explain their operation.

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Digital Electronics Question Paper of 3rd Semester ECE16 Download Previous Years Question Paper 2

9129

B.TECH. 3^RD SEMESTER

EC-205- DIGITAL ELECTORNICS

Time :3 hrs

Note : This paper consists of three sections. Section A is compulsory. Attempt any four questions form section B and two form Section C.

1.                  

a.                 List the advantages of  hexadecimal number system.

b.                 How will you detect overflow in signed-magnitude and Z’s complement integer additions.

c.                  Realize a z –input XOR gate using NAND gates only.

d.                 Simplify(A.B(C+B.D)+ A,B.) C.

e.                  What is meant by CAM ?

f.                   What do you understand by ‘race condition’ in flip-flops?

g.                 How many bits will a D/A converter use so that its full-scale output voltage is 5V and its 

            resolution is at the most 10mv.

h.                 Name the four triggering methods.

i.                   Define ‘propagation delay time’ and ‘figure of merit’

j.                   What are advantages of CMOS logic family over other logic families.

Section –B

2.                 Minimize the function using K-map method and implement the same using NAND/NOR 

            gates. F(A,B,C,D) = TTM (1,2,3,8,9,10,11,14). D(7,15)

3.                 What is a ROM? What are the different types of ROMs? Give the characteristics features of 

           each.

4.                 What is PLA? Design a  BCD to excess- 3 code converter using PLA.

5.                 Draw the circuit of a 3 – input ECL nor gate & discuss its operation what is the primary 

            advantages of ECL gate.

6.                 Devise a method of measuring frequency by means of a counter. Draw the circuit.

Section –C

7.                   

a.                 Convert a given Dflip- flop to a JK flip flop.

b.                 Discuss weighted resistor D/A converter.

8.                   

a.                 Design a synchronous mod – 6counter.

b.                 Realize the expression

           F(a,b,c,d) = Ʃm(0,2,3,6,8,9,12,14) using a 8:1 multiplexer and an inverter

9.              

      

a.                 Design a parity generator to generate an odd parity bit for a 4-bit word(Use minimum number            of gates)

b.                 Define a Register. Construct a shift register form RS flip-flops and explain their operation.

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Digital Electronics Question Paper of 3rd Semester ECE16 Download Previous Years Question Paper 1

Digital Electronics

(EC-205, DEC-2005)

Note: Section A is compulsory. Attempt any four questions from Section  and any two questions from  Section C.

Section-A

a) What is Excess-3 and Gray code?

b) Why ASCll-code is a 7-bit code?

c) Add (7F)16 & (BA)16.

d) Differentiate between half and full subtractors.

e) Compare a decoder with a demultiplexer.

f) What is meant by a state diagram?

g) What is meant by ‘accuracy’ of and A/D/converter

h) Difference between PLA and ROM?

i) Explain the problem of ‘current hogging’ in DCTL.

j) Explain the operation of CMOS(NOR gate).

Section-B

2. Represent the following decimal numbers in twos complement format:

 i) +3           ii) +25         iii) –5          iv) –11        v) –9

3. Write the full name in :a) ASCll code b) EBCDIC code c) Excess –3 code

4. Minimize the following function and realize using minimum no of gates:

 f1 = -Σm(0,3,5,6,9,10,12,15)

5. Design a BCD to Excess-3 code converter using minimum no of NAND gates

6. Design a four bit subtract or using four bit adder and minimum no of EX-OR gates.

Section-C

7. Obtain the output wave forms of a 5-stage ring-counter. Draw its state diagram

8. Explain the following codes and give example using four bits.

 a) CSB b)COB c)CTC d) CCD

9. Explain & compare the following with its block diagram.

a) Linear selection addressing

b) Coincidence selection addressing

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