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Wednesday, September 7, 2016

Roll No.
Total No. of Questions :09]
B.Tech. (Sem.-3rd)
Paper ID : [CS201]
Time : 03 Hours
Instruction to Candidates:
1) Section - A is Compulsory.
2) Attempt any Four questions from Section - B.
3) Attempt any Two questions from Section - C.

Section - A

1.     Choose the correct or best alternative in the following:
a.     Which logic is known as universal logic ?
                                                             i.      PAL logic
                                                           ii.      NAND logic
                                                        iii.      MUX logic
                                                        iv.      Decoder logic
b.     The time for which the   D-input of a D-FF must not change after the clock is applied is known as
                                                             i.      Hold time
                                                           ii.      Set-up time
                                                        iii.      Transition time
                                                        iv.      Delay-time
c.      How many memory chips of (128 x 8) are needed to provide a memory capacity of 4096 x 16?
                                                             i.      64
                                                           ii.      16
                                                        iii.      32
                                                        iv.      None of these
d.     In addition of two signed number, represented in 2’s complement form generates an overflow if.
                                                             i.      A. B = 0
                                                           ii.      A ± B=0
                                                        iii.      A ± B=1
                                                        iv.      A+B=1
Where A is the carry in to the sign bit position and B is the carry out the sign bit position.
e.      Addition of (1111)2  to a 4 bit binary number  ‘A’ result:-
                                                             i.      Incrementing A
                                                           ii.      Addition of (F)H
                                                        iii.      No change
                                                        iv.      Decrementing A
f.       In a microprocessor system, TRAP, HOLD, RESET pin got archived at the same time, while the processor was executing some instruction, then it will first respond to
                                                             i.      TRAP
                                                           ii.      HOLD
                                                        iii.      RESET
                                                        iv.      None
g.     Pseudo instructions are
                                                             i.      Machine instructions.
                                                           ii.      Logical instructions.
                                                        iii.      Micro instructions.
                                                        iv.      Instruction to assembler.
h.     An attempt to access a location not owned by a program is called
                                                             i.      Bus conflict.
                                                           ii.      Address fault.
                                                        iii.      page fault
                                                        iv.      operating system fault
i.       briefly write about 8255 chip.
j.       Compare SPMD and MIMD machine.

Section –B

2.     A RAM chip 4096 x 9 bits has two enble lines. How many pins are needed for the integrated circuit package? Draw a block diagram and label all input and outputs   pins of the RAM. What is the main feature of random access memory?
3.     The Ram IC as described above is used in a microprocessor system, having 16 bit address line and 8-bit data line. Enable- 1 input is active when A and A14 bits are 0 & 1 and enable-2 input is active when A13, A12  bits are ‘X’ and ‘O’. what shall be the range of addresses that is being used by the RAM.
4.     Give the comparison between & examples of hardwired control unit and micro programmed control unit.
5.     What do you mean by Fetch cycle, instruction Cycle, machine cycle, interrupt acknowledgement cycle.
6.     Design a CPU that meets the following specifications:
In can access 64 words of memory, each word being 8-bit long. The CPU does this by outputting a – bit address on its output pins A [5,….0] and reading in the 8-bit value from memory on inputs D [7,……0]. It has one 8-bit accumulator, 8-bit address register, 6-bit program counter, 2- bit instruction register, 8-bit data register.
The CPU must realize the following intrusion set:
Instruction            instruction Code   operation
ADD                    00AAAAAA        AC←AC+M[AAAAAA]
AND                     01AAAAAA        AC←AC M[AAAAAA]
JMP                      10AAAAAA        GO TO AAAAAA
INC                      11 xxxxxx            AC←AC +1

Section –C

a.     What do you mean by software & hardware interrupts? How these are used in a microprocessor system?
b.     What are the reasons of pipe-line conflicts in a pipe lined processor?
How are they resolved?
8.     Draw the block diagram of 8251 and transfer data from CPU to peripheral device at 9600 baud, 2 stop bits, even parity. Store 256 bytes of data at memory location my location

9.     What do you mean by initialization of DMA controller? How DMA controller works? Explain with suitable block diagram.


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