Roll No.

Total No. of Questions : 09

**B.Tech. (Sem.–3)**

**DIGITAL CIRCUITS & LOGIC DESIGN**

**Subject Code : CS-205**

**Paper ID : [CS205]**

Time : 3 Hrs.

Instruction to candidates :

1.
Section
–A is Compulsory.

2.
Attempt any Four questions from section –B

3.
Attempt any Two questions from section –C

**Section –A**

1.
Choose
the correct or best alternative in the following:

a.
8 is equal to signed binary number

i.
10001000

ii.
00001000

iii.
10000000

iv.
11000000

b.
De-Morgan’s first theorem shows the equivalence
of

i.
Or gate and exclusive OR gate.

ii.
NOR gate and Bubbled AND gate

iii.
NOR gate and NAND gate.

iv.
NAND gate and NOT gate.

c.
The digital logic family which has the lowest
propagation delay time is

i.
ECL.

ii.
TTL.

iii.
CMOS.

iv.
PMOS.

d.
The device which changes from serial data to
parallel data is

i.
COUNTER.

ii.
MULTIPLEXER

iii.
DEMULTIPLEXER

iv.
FLIP-FLOP

e.
A device which converts BCD to seven segment is
called

i.
Encoder.

ii.
Decoder

iii.
Multiplexer

iv.
Demultiplexer

f.
In successive –approximation A/D converter,
offset voltage equal to ½ LSB is added to the D/A converter’s output. This is
done to

i.
Improve the speed of operation.

ii.
Reduce the maximum quantization error.

iii.
Increase the number of bits at the output.

iv.
Increase the range of input voltage that can be
converted.

g.

i.
Convert 2222 in Hexadecimal number.

ii.
Subtract -27 from 68 using 2’s complements.

iii.
Divide(101110)

_{2}by (101)_{2}_{}

**Section –B**

2.
State and prove De-Morgan’s theorems.

3.
Prove the following identities using Boolean
algebra:

a.
(A+B)(A+AB)C +A(B+C)+ AB+ ABC= C(A+B)+ A(B+C)

b.
A(A.B) .B(A.B) =A ±B

c.
AB+ A+ AB=0

4.
A combinational circuit has 3 inputs A, B, C and
output F.F is true for following input combinations

A is false, B is true

A
is false, C is true

A B C are true

a.
Write the Truth table for F. use the convention
True= 1 and False =0

b.
Write the simplified expression for F in SOP
from

c.
Write the simplified expression for Fin POS from

d.
Draw logic circuit using minimum number of 2 –
input NAND gates.

5.
Minimize the logic function

F(A,B,C,D) = II M (1,2,3,8,9,10,11 ,14). d
(7,15)

Use Karnaugh map. Draw the logic circuit
for the simplified function using NOR gates only

6.
What is the necessity of interfacing in digital
ICs and what are the points to be kept in view, while interfacing between TTL
gate and CMOS gate?

**Section –C**

7.

a.
What is multiplexer Tree? Why it needed? Draw
the block diagram of a 32:1 Multiplexer Tree and explain, how is input directed
to the output in this system.

b.
What is a
Decoder? Compare a decoder and a demultiplexer with suitable block diagrams.

8.

a.
Draw the logic diagram of 4-bit Twisted Ring
counter and explain its operation with the help of timing diagram

b.
Design a MOD – 3 Susnchronous counter using J-K
flip-flops.

9.

a.
Differentiate between static MOS and Dynamic MOS
RAM. Draw the circuit of a static MOS RAM cell and explain its working.

b.
The
capacity of 2K x 16 PROM is to be expand to 16 K x 16. Find the number of PROM
chips required and the number of address lines in the expanded memory.

## 0 comments:

Post a Comment