## Digital Circuits And Logic Design Question Paper of 3rd Semester CSE74 Download Previous Years Question Paper 14

• Wednesday, September 07, 2016
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Roll No.
Total No. of Questions : 09
B.Tech.  (Sem.–3)
DIGITAL CIRCUITS & LOGIC DESIGN
Subject Code : CS-205
Paper ID : [A0453]
Time : 3 Hrs.
Instruction to candidates :
1. SECTION-A is COMPULSORY consisting of TEN questions carrying
TWO marks each.
2. SECTION-B contains FIVE questions carrying FIVE marks each and
students has to attempt any FOUR questions.
3. SECTION-C contains THREE questions carrying TEN marks each and
students has to attempt any TWO questions.

SECTION-A
l. Write briefly :
a) State DeMorgan’s theorems.
b) What is a Multiplexer Tree?
c) Differentiate Combinational and Sequential Circuits.
d) What do you mean by weighted code? Give example.
e) What is universal shift register?
f) How many flip flops are required for Mod-6 Counter?
g) Differentiate Static RAM and Dynamic RAM.
h) What is the importance of parity bit ?
i) Determine the resolution of the output from a DAC that has a 12-bit
input.
j) Differentiate Moore and Mealy Machines.

SECTION-B

2. What is a Decoder? Compare a decoder and a demultiplexer with suitable
block diagrams.

3. Draw the circuit of a counter type A-D converter and explain its operation.

4. Design a full adder circuit using NAND gates only.

5. Draw the circuit diagram of a mod-5 synchronous counter.

6. Simplify the following expression using K-Map :

f(A,B,C,D) = m(0, 3, 4, 5, 7, 8, 9) + d(10, 11, 12, 13, 14, 15) .

SECTION-C

7. What is Race around Condition? How it can be avoided? Also Discuss the working of Master Slave J-K Flip Flop.

8. Discuss the comparison of the important features of various IC logic families. Also draw and explain the operation of TTL NAND Gate.

9. Write a note on following :
a) Canonical POS
b) Boolean algebra.
c) Magnitude Comparator

d) Excess-3 Code